InitPeripheralClocks

DSP2833x_SysCtrl.c

위 파일에서 InitPeripheralClocks 함수가 있다.

이 함수에서는 HISPCP/LOSPCP 프리스케일 세팅뿐만 아니라 dsp28335에서 제공하는 각종 기능성 레지스터들의 기능 여부를 선택할 수 있다. 아래의 빨간 글씨 부분이다.

void InitPeripheralClocks(void)

{

   EALLOW;

// HISPCP/LOSPCP prescale register settings, normally it will be set to default values

   SysCtrlRegs.HISPCP.all = 0x0001; //HSPCLK=SYSCLKOUT/2=75MHz

   //SysCtrlRegs.LOSPCP.all = 0x0003; //LSPCLK=SYSCLKOUT/6=25MHz

   SysCtrlRegs.LOSPCP.all = 0x0002; //LSPCLK=SYSCLKOUT/4=37.5MHz

// XCLKOUT to SYSCLKOUT ratio.  By default XCLKOUT = 1/4 SYSCLKOUT

   // XTIMCLK = SYSCLKOUT/2

   XintfRegs.XINTCNF2.bit.XTIMCLK = 1;

   // XCLKOUT = XTIMCLK/2

   XintfRegs.XINTCNF2.bit.CLKMODE = 1;

   // Enable XCLKOUT

   XintfRegs.XINTCNF2.bit.CLKOFF = 0;

// Peripheral clock enables set for the selected peripherals.

// If you are not using a peripheral leave the clock off

// to save on power.

//

// Note: not all peripherals are available on all 2833x derivates.

// Refer to the datasheet for your particular device.

//

// This function is not written to be an example of efficient code.

   SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 1;    // ADC

   // *IMPORTANT*

   // The ADC_cal function, which  copies the ADC calibration values from TI reserved

   // OTP into the ADCREFSEL and ADCOFFTRIM registers, occurs automatically in the

   // Boot ROM. If the boot ROM code is bypassed during the debug process, the

   // following function MUST be called for the ADC to function according

   // to specification. The clocks to the ADC MUST be enabled before calling this

   // function.

   // See the device data manual and/or the ADC Reference

   // Manual for more information.

   ADC_cal();

   SysCtrlRegs.PCLKCR0.bit.I2CAENCLK = 0;   // I2C

   SysCtrlRegs.PCLKCR0.bit.SCIAENCLK = 1;   // SCI-A

   SysCtrlRegs.PCLKCR0.bit.SCIBENCLK = 1;   // SCI-B

   SysCtrlRegs.PCLKCR0.bit.SCICENCLK = 0;   // SCI-C

   SysCtrlRegs.PCLKCR0.bit.SPIAENCLK = 1;   // SPI-A

   SysCtrlRegs.PCLKCR0.bit.MCBSPAENCLK = 0; // McBSP-A

   SysCtrlRegs.PCLKCR0.bit.MCBSPBENCLK = 0; // McBSP-B

   SysCtrlRegs.PCLKCR0.bit.ECANAENCLK=0;    // eCAN-A

   SysCtrlRegs.PCLKCR0.bit.ECANBENCLK=0;    // eCAN-B

   SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;   // Disable TBCLK within the ePWM

   SysCtrlRegs.PCLKCR1.bit.EPWM1ENCLK = 1;  // ePWM1

   SysCtrlRegs.PCLKCR1.bit.EPWM2ENCLK = 0;  // ePWM2

   SysCtrlRegs.PCLKCR1.bit.EPWM3ENCLK = 0;  // ePWM3

   SysCtrlRegs.PCLKCR1.bit.EPWM4ENCLK = 0;  // ePWM4

   SysCtrlRegs.PCLKCR1.bit.EPWM5ENCLK = 0;  // ePWM5

   SysCtrlRegs.PCLKCR1.bit.EPWM6ENCLK = 0;  // ePWM6

   SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;   // Enable TBCLK within the ePWM

   SysCtrlRegs.PCLKCR1.bit.ECAP3ENCLK = 0;  // eCAP3

   SysCtrlRegs.PCLKCR1.bit.ECAP4ENCLK = 0;  // eCAP4

   SysCtrlRegs.PCLKCR1.bit.ECAP5ENCLK = 0;  // eCAP5

   SysCtrlRegs.PCLKCR1.bit.ECAP6ENCLK = 0;  // eCAP6

   SysCtrlRegs.PCLKCR1.bit.ECAP1ENCLK = 0;  // eCAP1

   SysCtrlRegs.PCLKCR1.bit.ECAP2ENCLK = 0;  // eCAP2

   SysCtrlRegs.PCLKCR1.bit.EQEP1ENCLK = 1;  // eQEP1

   SysCtrlRegs.PCLKCR1.bit.EQEP2ENCLK = 1;  // eQEP2

   SysCtrlRegs.PCLKCR3.bit.CPUTIMER0ENCLK = 1; // CPU Timer 0

   SysCtrlRegs.PCLKCR3.bit.CPUTIMER1ENCLK = 1; // CPU Timer 1

   SysCtrlRegs.PCLKCR3.bit.CPUTIMER2ENCLK = 0; // CPU Timer 2

   SysCtrlRegs.PCLKCR3.bit.DMAENCLK = 0;       // DMA Clock

   SysCtrlRegs.PCLKCR3.bit.XINTFENCLK = 1;     // XTIMCLK

   SysCtrlRegs.PCLKCR3.bit.GPIOINENCLK = 1;    // GPIO input clock

   EDIS;

}