void Init_SCIA()
{
SciaRegs.SCICCR.bit.STOPBITS = 0 ; // One Stop bit
SciaRegs.SCICCR.bit.PARITY = 0 ; // Odd parity(ignored)
SciaRegs.SCICCR.bit.PARITYENA = 0 ; // Parity disable
SciaRegs.SCICCR.bit.LOOPBKENA = 0 ; // loop back mode disable
SciaRegs.SCICCR.bit.ADDRIDLE_MODE = 0 ; // Idle-line mode (normal)
SciaRegs.SCICCR.bit.SCICHAR = 0x07 ; // SCI char-length 8 bit
SciaRegs.SCICTL1.bit.RXERRINTENA = 1 ; // SCI receive error interrupt disable
SciaRegs.SCICTL1.bit.SWRESET = 0 ; // SCI module reset
asm(" RPT #10 || nop ") ;
SciaRegs.SCICTL1.bit.SWRESET = 1 ; // SCI mdoule reset release
SciaRegs.SCICTL1.bit.TXWAKE = 0 ; // SCI transmitter wake-up method (non use)
SciaRegs.SCICTL1.bit.SLEEP = 0 ; // SCI sleep mode non use
SciaRegs.SCICTL1.bit.TXENA = 1 ; // SCI transmitter enable
SciaRegs.SCICTL1.bit.RXENA = 1 ; // SCI receiver enable
// SciaRegs.SCIHBAUD = 0x01 ; // ( 37.5M / (9600 * 8) ) - 1 = 0x01e7
// SciaRegs.SCILBAUD = 0xe7 ;
SciaRegs.SCIHBAUD = 0x00 ; // ( 37.5M / (38400 * 8 ) - 1 = 0x0079
SciaRegs.SCILBAUD = 0x79 ;
// SciaRegs.SCIHBAUD = 0x00 ; // ( 37.5M / (57600 * 8) ) - 1 = 0x0050
// SciaRegs.SCILBAUD = 0x50 ;
SciaRegs.SCICTL2.bit.RXBKINTENA = 1 ; // Receive buffer or break interrup enable
SciaRegs.SCICTL2.bit.TXINTENA = 1 ; // SCITXBUF-register interrupt enable
SciaRegs.SCIFFTX.bit.SCIRST = 1 ; // SCI FIFO can resume transmit or receive
SciaRegs.SCIFFTX.bit.SCIFFENA = 0 ; // SCI FIFO enhancements are enable
SciaRegs.SCIFFTX.bit.TXFIFOXRESET = 0 ; // Transmitter FIFO Re-Enable (FIFO Point to zero reset)
SciaRegs.SCIFFTX.bit.TXFFIENA = 0 ; // Transmitter FIFO Interrupt enable
SciaRegs.SCIFFTX.bit.TXFFILIL = 0 ; // Transmitter FIFO deep level (5)
SciaRegs.SCIFFRX.bit.RXFIFORESET = 0 ; // Receive FIFO Re-Enable
SciaRegs.SCIFFRX.bit.RXFFIENA = 0 ; // Receive FIFO Interrupt Enable
SciaRegs.SCIFFRX.bit.RXFIFST = 4; // RX FIFO 4개로 함
SciaRegs.SCIFFRX.bit.RXFFIL = 0 ; // Receive FIFO deep level (5)
}
void Init_SCIB()
{
ScibRegs.SCICCR.bit.STOPBITS = 0 ; // One Stop bit
ScibRegs.SCICCR.bit.PARITY = 0 ; // Odd parity(ignored)
ScibRegs.SCICCR.bit.PARITYENA = 0 ; // Parity disable
ScibRegs.SCICCR.bit.LOOPBKENA = 0 ; // loop back mode disable
ScibRegs.SCICCR.bit.ADDRIDLE_MODE = 0 ; // Idle-line mode (normal)
ScibRegs.SCICCR.bit.SCICHAR = 0x07 ; // SCI char-length 8 bit
ScibRegs.SCICTL1.bit.RXERRINTENA = 1 ; // SCI receive error interrupt disable
ScibRegs.SCICTL1.bit.SWRESET = 0 ; // SCI module reset
asm(" RPT #10 || nop ") ;
ScibRegs.SCICTL1.bit.SWRESET = 1 ; // SCI mdoule reset release
ScibRegs.SCICTL1.bit.TXWAKE = 0 ; // SCI transmitter wake-up method (non use)
ScibRegs.SCICTL1.bit.SLEEP = 0 ; // SCI sleep mode non use
ScibRegs.SCICTL1.bit.TXENA = 1 ; // SCI transmitter enable
ScibRegs.SCICTL1.bit.RXENA = 1 ; // SCI receiver enable
// ScibRegs.SCIHBAUD = 0x01 ; // ( 37.5M / (9600 * 8) ) - 1 = 0x01e7
// ScibRegs.SCILBAUD = 0xe7 ;
ScibRegs.SCIHBAUD = 0x00 ; // ( 37.5M / (38400 * 8 ) - 1 = 0x0079
ScibRegs.SCILBAUD = 0x79 ;
// ScibRegs.SCIHBAUD = 0x00 ; // ( 37.5M / (57600 * 8) ) - 1 = 0x0050
// ScibRegs.SCILBAUD = 0x50 ;
ScibRegs.SCICTL2.bit.RXBKINTENA = 1 ; // Receive buffer or break interrup enable
ScibRegs.SCICTL2.bit.TXINTENA = 1 ; // SCITXBUF-register interrupt enable
ScibRegs.SCIFFTX.bit.SCIRST = 1 ; // SCI FIFO can resume transmit or receive
ScibRegs.SCIFFTX.bit.SCIFFENA = 0 ; // SCI FIFO enhancements are enable
ScibRegs.SCIFFTX.bit.TXFIFOXRESET = 0 ; // Transmitter FIFO Re-Enable (FIFO Point to zero reset)
ScibRegs.SCIFFTX.bit.TXFFIENA = 0 ; // Transmitter FIFO Interrupt enable
ScibRegs.SCIFFTX.bit.TXFFILIL = 0 ; // Transmitter FIFO deep level (5)
ScibRegs.SCIFFRX.bit.RXFIFORESET = 0 ; // Receive FIFO Re-Enable
ScibRegs.SCIFFRX.bit.RXFFIENA = 0; // Receive FIFO Interrupt Enable
ScibRegs.SCIFFRX.bit.RXFFIL = 0 ; // Receive FIFO deep level (5)
}